TL;DR
A developer has successfully ported the Project Oberon operating system to RISC-V architecture, replacing the original RISC-5. This development demonstrates the OS’s adaptability to modern hardware, with potential implications for educational and research uses.
A developer has shared a version of the Project Oberon operating system that runs on RISC-V hardware, replacing the original RISC-5 architecture. This port demonstrates the OS’s adaptability beyond its initial design, highlighting ongoing efforts to modernize and extend its use.
The port was shared via a Show HN post, indicating a community-driven project rather than an official release. The developer detailed the process of adapting Oberon to RISC-V, including modifications to the system’s hardware interface and kernel components. The effort involved significant low-level work, given the differences between RISC-5 and RISC-V architectures.
While the original Oberon system was designed for a specific RISC-5 processor used in the Oberon hardware platform, the port demonstrates that the system’s codebase can be adapted to modern open-source hardware. The developer has provided source code and instructions, making this a potentially valuable resource for educational institutions and researchers interested in operating system portability and minimalistic OS design.
Implications for OS Portability and Education
This development underscores the flexibility of the Oberon OS and its potential to run on modern hardware architectures like RISC-V. For educators and researchers, it offers an opportunity to study a minimalist OS on open hardware, fostering experimentation and learning. It also highlights the ongoing relevance of Oberon’s design principles in contemporary computing contexts.
ESP32-C5 5GHz/2.4GHz Dual-Band Wi-Fi 6 Dev Board, ESP32-C5-WROOM-1 Module, Support WiFi/BLE 5/ Zigbee/Thread/Wireless Communications, 240MHz RISC-V Processor, 16MB Flash+8MB PSRAM, with Pin Header
- Processor: RISC-V 32-bit, up to 240MHz
- Memory: 16MB Flash, 8MB PSRAM
- Wireless Support: Wi-Fi 6, BLE 5, Zigbee, Thread
As an affiliate, we earn on qualifying purchases.
As an affiliate, we earn on qualifying purchases.
Background on Project Oberon and RISC-V Adaptations
Project Oberon was originally developed by Niklaus Wirth and colleagues at ETH Zurich as both a programming language and an operating system, primarily for custom hardware based on the RISC-5 architecture. Over the years, Oberon has been recognized for its simplicity and educational value.
RISC-V, an open-source hardware instruction set architecture, has gained widespread interest for its flexibility and modern design. Porting legacy systems like Oberon to RISC-V aligns with broader efforts to modernize and democratize hardware and software development. Prior to this, Oberon was mostly confined to its original hardware environment, limiting its broader adoption.
The recent port, shared via a Show HN post, represents a community effort to extend Oberon’s reach onto more accessible hardware platforms, potentially enabling wider experimentation and use.
“Porting Oberon to RISC-V was a challenging but rewarding process, demonstrating the system’s adaptability and the potential for modern hardware support.”
— the developer who shared the port
Extent of Compatibility and Performance on RISC-V
It is not yet clear how fully the ported Oberon system supports all hardware features of RISC-V or how it performs compared to the original RISC-5 version. Details on stability, peripheral support, and usability are still emerging, and further testing is needed to confirm operational readiness.
Next Steps for Testing and Community Involvement
Developers and users are expected to conduct more extensive testing of the RISC-V port, including hardware compatibility and performance benchmarks. The source code and instructions are publicly available, inviting community contributions to improve stability and expand hardware support. Future updates may include porting to different RISC-V boards and integrating additional features.
Key Questions
What is Project Oberon?
Project Oberon is both a programming language and an operating system developed at ETH Zurich, designed for simplicity and educational use, originally for custom RISC-5 hardware.
Why is porting Oberon to RISC-V significant?
This port demonstrates the system’s adaptability to modern, open-source hardware architectures, potentially broadening its educational and practical applications.
Is the port fully functional?
It is still in early stages; full hardware support, peripheral compatibility, and stability are under testing. Further development is expected.
Can I try this port myself?
Yes, the source code and instructions are publicly available via the developer’s Show HN post, inviting community testing and improvement.
What are the future plans for this project?
Next steps include extensive testing, optimizing performance, expanding hardware compatibility, and potentially porting to additional RISC-V boards.
Source: hn
